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general description the max3873a is a compact, low-power 2.488gbps/ 2.67gbps clock-recovery and data-retiming ic for sdh/sonet applications. the phase-locked loop (pll) recovers a synchronous clock signal from the serial nrz data input. the input data is then retimed by this recovered clock, providing a clean data output. the max3873a meets all sdh/sonet jitter specifications, does not require an external reference clock to aid in frequency acquisition, and provides excellent tolerance to both deterministic and sinusoidal jitter. the max3873a provides a pll loss-of-lock ( lol ) output to indicate whether the cdr is in lock. the recovered data and clock outputs are cml with on-chip 50 ? back termi- nations on each line. the clock output can be powered down if not used. the max3873a is implemented in maxim? second- generation sige process and consumes only 260mw at 3.3v supply (output clock disabled, low output swing). the device is available in a 4mm x 4mm 20-pin qfn exposed-pad package and operates from -40? to +85?. applications switch matrix backplanes sdh/sonet receivers and regenerators add/drop multiplexers digital cross-connects sdh/sonet test equipment dwdm transmission systems features ? fully integrated clock recovery and data retiming ? power dissipation: 260mw with +3.3v supply ? clock jitter generation: 5mui rms ? exceeds ansi, itu, and bellcore sdh/sonet jitter specifications ? differential input range: 50mv p-p to 1.6v p-p ? single +3.3v power supply ? pll fast track (fastrack) mode available ? clock output can be disabled ? input data rate: 2.488gbps or 2.67gbps ? selectable output amplitude ? tolerates 2000 consecutive identical digits ? loss-of-lock indicator ? differential cml data and clock outputs ? operating temperature range: -40? to +85? max3873a low-power, compact 2.5gbps/2.7gbps clock-recovery and data-retiming ic ________________________________________________________________ maxim integrated products 1 19-2577; rev 1; 5/03 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. ordering information typical application circuit appears at end of data sheet. 20 19 18 17 16 gnd fil+ fil- gnd lol 6 7 8 9 10 v cc fastrack vcc_vco mode sclken 11 12 13 14 15 **note: the exposed pad must be soldered to the supply ground. sclko- sclko+ vcc_buf sdo- sdo+ 5 4 3 2 1 v cc sdi- sdi+ v cc rateset max3873a qfn** top view pin configuration part t em p r an g e pin- package pk g code m ax 3873ae g p - 40c to + 85c 20 qfn ( 4mm x 4m m ) g2044
max3873a low-power, compact 2.5gbps or 2.7gbps clock-recovery and data-retiming ic 2 _______________________________________________________________________________________ absolute maximum ratings dc electrical characteristics (v cc = 3.0v to 3.6v, t a = -40? to +85?. typical values are at 2.488gbps, v cc = 3.3v, t a = +25?, unless otherwise noted.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. supply voltage, v cc ..............................................-0.5v to +5.0v voltage at sdi .............................. (v cc - 1.0v) to (v cc + 0.5v) cml output current at sdo? sclko ............................22ma voltage at lol , fastrack, fil? sclken mode, rateset...................................-0.5v to (v cc + 0.5v) continuous power dissipation (t a = +85?) 20-lead qfn (derate 20.0mw/? above +85?) .....1300mw operating temperature range ...........................-40? to +85? storage temperature range .............................-50? to +150? processing temperature..................................................+400? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units mode = gnd, sclken = low 79 99 supply current (note 2) i cc mode = open, sclken = high 112 142 ma cml input specifications (sdi+, sdi-) differential input voltage v id figure 1 50 1600 mv p-p single-ended input voltage v is figure 1 v cc - 0.8 v cc + 0.4 v input common-mode voltage dc-coupled, figure 1 v cc - v id /4 v input termination to v cc r in 40 50 60 ? cml output specifications (sdo+, sdo-, sclko+, sclko-) mode = open 640 800 1000 mode = v cc 400 600 800 differential output swing (note 3) mode = gnd 200 400 600 mv p-p differential output resistance r o 80 100 120 ? mode = open v cc - 0.17 mode = v cc v cc - 0.13 output common-mode voltage (note 3) mode = gnd v cc - 0.08 v ttl input/output specifications (fastrack, lol, sclken, mode, rateset) input high voltage v ih 2.0 v input low voltage v il 0.8 v input current -30 +30 ? output high voltage v oh i oh = sourcing 40? 2.4 v output low voltage v ol i ol = sinking 2ma 0.4 v
max3873a low-power, compact 2.5gbps or 2.7gbps clock-recovery and data-retiming ic _______________________________________________________________________________________ 3 ac electrical characteristics (v cc = 3.0v to 3.6v, c f = 0.022?, t a = -40? to +85?. typical values are at v cc = 3.3v, 2.488gbps, t a = +25?, unless otherwise noted.) (note 4) parameter symbol conditions min typ max units rateset = low 2.488 serial input data rate rateset = high 2.67 gbps clock-to-q delay t clk-q figure 2 (note 5) -70 +70 ps jitter peaking j p f 2mhz 0.1 db jitter transfer bandwidth j bw rateset = low 2.0 mhz f = 70khz, 0.4ui deterministic jitter on input data 6.9 f = 100khz, 0.4ui deterministic jitter on input data 2.12 4.5 f = 1mhz, 0.4ui deterministic jitter on input data 0.33 0.6 (notes 6, 8) f = 10mhz, 0.4ui deterministic jitter on input data 0.15 0.3 f = 70khz, 0.4ui deterministic jitter on input data 6.9 f = 100khz, 0.4ui deterministic jitter on input data 2.12 4.5 f = 1mhz, 0.4ui deterministic jitter on input data 0.33 0.6 sinusoidal jitter tolerance (notes 6, 9) f = 10mhz, 0.37ui deterministic jitter on input data 0.15 0.3 ui p-p 5 6.8 mui rms (notes 7, 8) 45 62 mui p-p 6 7.65 mui rms jitter generation j gen (notes 7, 9) 40 86 mui p-p clock output edge speed 20% to 80% 60 110 ps data output edge speed 20% to 80% 60 110 ps tolerated consecutive identical digits 2000 bits 100khz to 2.5ghz 17 sdi?input return loss (-20log( ? s 11 ? )) 2.5ghz to 4.0ghz 14 db frequency acquisition time figure 4 1 ms ? lol assert time figure 4 1.6
max3873a low-power, compact 2.5gbps or 2.7gbps clock-recovery and data-retiming ic 4 _______________________________________________________________________________________ figure 1. definition of input voltage swing figure 2. definition of clock-to-q delay (a) ac-coupled single-ended input (cml or pecl) (b) dc-coupled single-ended cml input 25mv 25mv 800mv 800mv v cc + 0.4v v cc v cc - 0.4v v cc v cc - 0.4v v cc - 0.8v sclko+ sdo t clk t clk-q figure 4. definition of lol assert time and frequency acquisition time input data frequency acquisition time lol output lol assert time figure 3. definition of phase acquisition time serial data 1200 bits of 1? pattern <2 s f astrack d ata vco clock phase aligned to input data ac electrical characteristics (continued) (v cc = 3.0v to 3.6v, c f = 0.022?, t a = -40? to +85?. typical values are at v cc = 3.3v, 2.488gbps, t a = +25?, unless otherwise noted.) (note 4) note 1: at t a = -40?, dc characteristics are guaranteed by design and characterization. note 2: cml outputs open. note 3: r l = 50 ? to v cc . note 4: ac characteristics are guaranteed by design and characterization. note 5: relative to the falling edge of sclko+. see figure 2. note 6: measured with 2 23 - 1 prbs. note 7: jitter bw = 12khz to 20mhz. note 8: rateset = low. note 9: rateset = high.
max3873a low-power, compact 2.5gbps or 2.7gbps clock-recovery and data-retiming ic _______________________________________________________________________________________ 5 recovered clock and data (2.488gbps, 2 23 - 1 pattern, v in = 50mv p-p ) max3873a toc01 125mv/div 100ps/div recovered clock and data (2.67gbps, 2 23 - 1 pattern, v in = 50mv p-p ) max3873a toc02 125mv/div 100ps/div recovered clock jitter (2.488gbps) max3873a toc03 10ps/div 2 23 - 1 pattern rms = 2.0ps rms 100 10 1 0.1 10 100 1000 10,000 jitter tolerance (2.488gbps, 2 23 - 1 pattern, v in = 50mv p-p ) max3873a toc04 jitter frequency (khz) input jitter (uip-p) bellcore mask with 0.2ui of pwd with 0.4ui of deterministic jitter 0 60 40 20 80 100 120 140 160 180 200 -50 0 -25 25 5 075100 supply current vs. temperature (sclko disabled) max3873a toc06 temperature ( c) supply current (ma) med output swing max output swing min output swing 0 60 40 20 80 100 120 140 160 180 200 -50 0 -25 25 5 075 100 supply current vs. temperature (sclko enabled) max3873a toc07 temperature ( c) supply current (ma) med output swing max output swing min output swing t ypical operating characteristics (t a = +25?, unless otherwise noted.) 0.5 -3.0 jitter transfer -1.5 max3873a toc05 frequency (hz) transfer (db) -1.0 -0.5 0 10 3 10 5 10 6 10 4 10 7 -2.0 -2.5 bellcore mask
max3873a low-power, compact 2.5gbps or 2.7gbps clock-recovery and data-retiming ic 6 _______________________________________________________________________________________ t ypical operating characteristics (continued) (t a = +25?, unless otherwise noted.) 2.0 2.3 2.2 2.1 2.4 2.5 2.6 2.7 2.8 2.9 3.0 -50 0 50 100 pullin range (rateset = 0) max3873a toc08 ambient temperature ( c) frequency (ghz) 10 -2 10 -3 10 -4 10 -5 10 -6 10 -7 bit-error ratio vs. input amplitude max3873a toc09 input voltage (mvp-p) bit error ratio 012345 10 -8 10 -9 10 -10 0 0.3 0.2 0.1 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.05 0.10 0.15 0.20 jitter tolerance vs. input deterministic jitter max3873a toc10 deterministic jitter (ui p-p ) sinusoidal jitter tolerance (ui p-p ) f jitter = 1mhz f jitter = 10mhz prbs = 2 23 - 1 0 0.2 0.1 0.4 0.3 0.6 0.5 0.7 0.9 0.8 1.0 -40 -20 -10 -30 0 10 20 30 40 jitter tolerance vs. pulse-width distortion max3873a toc11 input pulse-width distortion (%) sinusoidal jitter tolerance (ui p-p ) prbs = 2 23 - 1 f jitter = 1mhz f jitter = 10mhz input data filtered by 1870mhz 4th-order bessel filter pin name function 1 rateset input rate select. connect to ttl low for 2.488gbps data and to ttl high for 2.67gbps data. 2, 5, 6 v cc 3.3v supply voltage 3 sdi+ positive serial data input 4 sdi- negative serial data input 7 fastrack pll fast track control, ttl input. when fastrack is ttl high, the pll is switched to a fast- track mode for fast phase acquisition. when fastrack is ttl low, the pll operates normally. 8 vcc_vco 3.3v vco supply voltage 9 mode output amplitude mode select. mode = open sets the cml output amplitude to high; mode = high sets the output amplitude to medium; mode = low sets the output amplitude to low. pin description
max3873a low-power, compact 2.5gbps or 2.7gbps clock-recovery and data-retiming ic _______________________________________________________________________________________ 7 detailed description the max3873a consists of a fully integrated phase- locked loop (pll), input amplifier, and cml output buffers (figure 5). the pll consists of a phase/fre- quency detector, a loop filter, and a voltage-controlled oscillator (vco). this device is designed to deliver the best combination of jitter performance and power dissipation by using a fully differential signal architecture and low-noise design techniques. input amplifier the input amplifier provides internal 50 ? line termina- tions and can accept a differential input amplitude from 50mv p-p to 1600mv p-p . the structure of the input amplifier is shown in figure 9. phase detector the phase detector incorporated in the max3873a pro- duces a voltage proportional to the phase difference between the incoming data and the internal clock. because of its feedback nature, the pll drives the error voltage to zero, aligning the recovered clock to the center of the incoming data eye for retiming. frequency detector the digital frequency detector (fd) aids frequency acquisition during startup conditions. the frequency difference between the received data and the vco clock is derived by sampling the vco outputs on each edge of the data input signal. the fd drives the vco until the frequency difference is reduced to zero. once frequency acquisition is complete, the fd returns to a neutral state. loop filter and vco the phase detector and frequency detector outputs are summed into the loop filter. an external capacitor, c f , is required to set the pll damping ratio. see the design procedure section for guidelines on selecting this capacitor. pin name function 10 sclken c l ock outp ut e nab l e, ttl inp ut. w hen s c lke n = op en or s c lke n = hi g h, the cl ock outp uts ( s c lko ) ar e enab l ed . w hen s c lke n = l ow , the cl ock outp uts ar e d i sab l ed and s c lko ? = v cc . 11 sclko- negative clock output, cml. this output can be disabled by setting sclken to low. 12 sclko+ positive clock output, cml. this output can be disabled by setting sclken to low. 13 vcc_buf 3.3v cml output buffer supply voltage 14 sdo- negative data output, cml 15 sdo+ positive data output, cml 16 lol loss-of-lock output, ttl (active low). the lol output indicates a pll lock failure. 17, 20 gnd supply ground 18 fil- negative pll loop filter connection. connect a 0.022? capacitor between fil+ and fil-. 19 fil+ positive pll loop filter connection. connect a 0.022? capacitor between fil+ and fil-. ep exposed pad ground. the exposed pad must be soldered to the circuit board ground for proper electrical and thermal operation. pin description (continued) figure 5. functional diagram rateset fil- fil+ gnd v cc max3873a loop filter fastrack sdo+ sdo- sdi+ sdi- sclko+ sclko- sclken mode amp amp amp i q phase and frequency detector lol vco
max3873a low-power, compact 2.5gbps or 2.7gbps clock-recovery and data-retiming ic 8 _______________________________________________________________________________________ the loop filter output controls the on-chip lc vco run- ning at either 2.488ghz or 2.67ghz. the vco provides low phase noise and is trimmed to the correct frequency. cl ock jitter generation is typically 2ps rms within a jitter band of 12khz to 20mhz. loss-of-lock monitor a loss-of-lock ( lol ) monitor is incorporated in the max3873a to indicate either a loss of frequency lock or the absence of incoming data. under loss-of-lock con- ditions, lol may momentarily assert high due to noise. design procedure setting the loop filter the max3873a is designed for both regenerator and receiver applications. its fully integrated pll is a classic second-order feedback system, with a loop bandwidth (j bw ) below 2.0mhz. the external capacitor, c f , can be adjusted to set the loop damping. figures 6 and 7 show the open-loop and closed-loop transfer functions. the pll zero frequency, f z , is a function of external capacitor c f and can be approximated according to: with c f expressed in f. for an overdamped system, the jitter peaking (j p ) of a second-order system can be approximated by: for example, using c f = 2000pf results in jitter peaking of 0.2db. reducing c f below 500pf might result in pll instability. the recommended value is c f = 0.022? to guarantee a maximum jitter peaking of less than 0.1db. c f must be a low tc, high-quality capacitor of type x7r or better. fastrack mode the max3873a has a pll fast-track (fastrack) mode to decrease locking time in switched data applications. in applications where the input data is switched from one source to another, there is a brief period in which there is no valid data input to the max3873a. in the absence of input data, the pll phase slowly drifts from the ideal position. by enabling fastrack during reacquisition, the time required to regain phase alignment is reduced. this is accomplished by increasing the loop bandwidth by approximately 50%. the bandwidth of the max3873a is also linearly depen- dent upon the transition density of the input data. by using a preamble of 1200 bits of a 1? pattern during switching, the loop bandwidth is increased by a factor of approxi- mately 2 (figure 3). thus, by using a 1? pattern pream- ble and enabling fastrack, the pll bandwidth is increased by a factor of approximately 3, resulting in the fastest possible reacquisition of phase lock. fastrack increases the rate at which the max3873a acquires the proper phase, assuming that the vco is already running at the proper frequency. on startup con- ditions, however, the vco frequency is significantly differ- ent from the input data, and the time required to lock to the incoming data is increased to approximately 1.0ms. j f j p z bw log =+ ? ? ? ? ? ? 20 1 f c z f () = ? 1 2 3000 figure 6. open-loop transfer function figure 7. closed-loop transfer function c f = 0.022 f f z = 2.4khz c f = 2000pf f z = 26khz h o (j2 f) (db) open-loop gain 1000 f (khz) 100 10 1 c f = 0.022 f h(j2 f) (db) 1000 100 10 1 f (khz) -3 0 closed-loop gain c f = 2000pf
max3873a low-power, compact 2.5gbps or 2.7gbps clock-recovery and data-retiming ic _______________________________________________________________________________________ 9 sinusoidal jitter tolerance and input deterministic jitter trade-offs the max3873a has excellent jitter tolerance. adding dj to the input will close the eye opening and result in reduced sinusoidal jitter tolerance. it typically can toler- ate more than 0.3ui p-p of 10mhz jitter when measured with a 2 23 - 1 prbs data stream with 0.4ui of determin- istic jitter (dj). this gives a total high-frequency jitter tol- erance of 0.7ui. refer to the jitter tolerance vs. pulse-width distortion and jitter tolerance vs. deterministic jitter graphs in the typical operating characteristics section. input and output terminations the max3873a? digital cml outputs (sdo+, sdo-, sclko+, sclko-) have selectable output amplitude controlled by the mode input. if the sclko outputs are not used, they can be disabled (see the supply current vs. temperature graph in the typical operating characteristics section). the structure of the high-speed digital outputs is shown in figure 8. the mode input sets the current in the cur- rent source, thereby controlling the output swing. the sclken input sets the current in the sclko current source to 0ma, disabling the output. the structure of the cml inputs (sdi? is shown in figure 9. unless the cml input is dc-coupled to a cml output, use ac-coupling with the cml inputs to avoid upsetting the common-mode voltage. applications information consecutive identical digits (cid) the max3873a has a low phase and frequency drift in the absence of data transitions. as a result, long runs of consecutive zeros and ones can be tolerated while maintaining a ber of less than 10 -10 . the cid tolerance is tested using a 2 13 - 1 prbs, substituting a long run of zeros to simulate the worst case. a cid tolerance of 2000 bits is typical. exposed-pad package the exposed-pad (ep), 20-pin qfn incorporates fea- tures that provide a very low thermal-resistance path for heat removal from the ic. the pad is electrical ground on the max3873a and must be soldered to the circuit board for proper thermal and electrical performance. layout circuit board layout and design can significantly affect the max3873a? performance. use good high-frequency design techniques, including minimizing ground induc- tance and using controlled-impedance transmission lines on the data and clock signals. place power-supply decoupling as close to the v cc pins as possible. isolate the input from the output signals to reduce feedthrough. max3873a sdi+ 50 ? sdi- v cc v cc v cc 50 ? max3873a out- mode sclken sclko only out+ v cc 50 ? 50 ? figure 8. cml output model figure 9. cml input model
max3873a low-power, compact 2.5gbps or 2.7gbps clock-recovery and data-retiming ic 10 ______________________________________________________________________________________ chip information transistor count: 2028 process: sige bicmos max3873a cdr sdi+ fil+ fil- lol mode sdi- fastrack sdo+ sdo- sclko+ sclko- sclken 20-pin qfn max3873a switch card 2.5gbps optical transceiver rateset crosspoint switch t ypical application circuit
max3873a low-power, compact 2.5gbps or 2.7gbps clock-recovery and data-retiming ic ______________________________________________________________________________________ 11 12,16,20, 24l qfn.eps e 1 2 21-0106 package outline 12,16,20,24l qfn, 4x4x0.90 mm package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)
max3873a low-power, compact 2.5gbps or 2.7gbps clock-recovery and data-retiming ic maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2003 maxim integrated products printed usa is a registered trademark of maxim integrated products. e 2 2 21-0106 package outline 12,16,20,24l qfn, 4x4x0.90 mm package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)

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